Power, Reset, and Clock Management
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8.1.12.3.8 CM_CPTS_RFT_CLKSEL Register (offset = 20h) [reset = 0h]
CM_CPTS_RFT_CLKSEL is shown in Figure 8-145 and described in Table 8-154.
Selects the Mux select line for CPTS RFT clock [warm reset insensitive]
Figure 8-145. CM_CPTS_RFT_CLKSEL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved Reserved Reserved CLKSEL
R-0h R-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-154. CM_CPTS_RFT_CLKSEL Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
2 Reserved R 0h
1 Reserved R 0h
0 CLKSEL R/W 0h
Selects the Mux select line for cpgmac rft clock [warm reset
insensitive]
0x0 = SEL1 : Selects CORE_CLKOUTM5
0x1 = SEL2 : Selects CORE_CLKOUTM4
682
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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