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17.1.5.1 REVISION Register (offset = 0h) [reset = 400h]
REVISION is shown in Figure 17-3 and described in Table 17-15.
This register contains the IP revision code
Figure 17-3. REVISION Register
31 30 29 28 27 26 25 24
SCHEME RES FUNC
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
FUNC
R-0h
15 14 13 12 11 10 9 8
RTL MAJOR
R-0h R-4h
7 6 5 4 3 2 1 0
Custom MINOR
R-10h R-400h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-15. REVISION Register Field Descriptions
Bit Field Type Reset Description
31-30 SCHEME R 0h
Not defined yet
29-28 RES R 0h
Reserved
27-16 FUNC R 0h
Not defined yet
15-11 RTL R 0h
Not defined yet
10-8 MAJOR R 4h
IP-Major Revision
7-6 Custom R 10h
Not Defined Yet
5-0 MINOR R 400h
IP-Minor Revision
3248
Interprocessor Communication SPRUH73H–October 2011–Revised April 2013
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