Interrupt Controller Registers
www.ti.com
6.5.1.13 INTC_MIR0 Register (offset = 84h) [reset = FFFFFFFFh]
INTC_MIR0 is shown in Figure 6-16 and described in Table 6-16.
This register contains the interrupt mask
Figure 6-16. INTC_MIR0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mir
R/W-FFFFFFFFh
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-16. INTC_MIR0 Register Field Descriptions
Bit Field Type Reset Description
31-0 Mir R/W FFFFFFFFh
Interrupt mask
218
Interrupts SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
