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Interrupt Controller Registers
6.5.1.4 INTC_SIR_IRQ Register (offset = 40h) [reset = FFFFFF80h]
INTC_SIR_IRQ is shown in Figure 6-7 and described in Table 6-7.
This register supplies the currently active IRQ interrupt number.
Figure 6-7. INTC_SIR_IRQ Register
31 30 29 28 27 26 25 24
SpuriousIRQ
R/W-1FFFFFFh
23 22 21 20 19 18 17 16
SpuriousIRQ
R/W-1FFFFFFh
15 14 13 12 11 10 9 8
SpuriousIRQ
R/W-1FFFFFFh
7 6 5 4 3 2 1 0
SpuriousIRQ ActiveIRQ
R/W-1FFFFFFh R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-7. INTC_SIR_IRQ Register Field Descriptions
Bit Field Type Reset Description
31-7 SpuriousIRQ R/W 1FFFFFFh
Spurious IRQ flag
6-0 ActiveIRQ R/W 0h
Active IRQ number
209
SPRUH73H–October 2011–Revised April 2013 Interrupts
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