Initialization
__main()
(stack setup)
main()
Booting
DPLLs and clocks
configurations
System start-up
MPU WDT1 setup
Functional Description
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Figure 26-5. ROM Code Startup Sequence
Upon system startup, the CPU performs the public-side initialization and stack setup (compiler auto
generated C- initialization or “scatter loading”). Then it configures the watchdog timer 1 (set to three
minutes), performs system clocks configuration. Finally it jumps to the booting routine.
26.1.4.2 CPU State at Public Startup
The CPU L1 instruction cache and branch prediction mechanisms are not activated as part of the
public boot process. The public vector base address is configured to the reset vector of Public ROM Code
(20000h). MMU is left switched off during the public boot (hence L1 data cache off).
26.1.4.3 Clocking Configuration
The device supports the following frequencies based on SYSBOOT[15:14]
Table 26-5. Crystal Frequencies Supported
SYSBOOT[15:14] Crystal Frequency
00b 19.2 MHz
01b 24 MHz
10b 25 MHz
11b 26 MHz
The ROM Code configures the clocks and DPLLs which are necessary for ROM Code execution:
• L3 ADPLLS locked to provide 200MHz clocks for peripheral blocks.
• DDR DPLL locked to provide 400MHz.
• MPU ADPLLS is locked to provide 500 MHz for the A8.
• PER ADPLLLJ is locked to provide 960MHz and 192MHz for peripheral blocks.
4102
Initialization SPRUH73H–October 2011–Revised April 2013
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