Enhanced Capture (eCAP) Module
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15.3.4.1.2 CTRPHS Register (offset = 4h) [reset = 0h]
CTRPHS is shown in Figure 15-117 and described in Table 15-110.
Figure 15-117. CTRPHS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTRPHS
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 15-110. CTRPHS Register Field Descriptions
Bit Field Type Reset Description
31-0 CTRPHS R/W 0h Counter phase value register that can be programmed for phase
lag/lead.
This register shadows TSCTR and is loaded into TSCTR upon either
a SYNCI event or S/W force via a control bit.
Used to achieve phase control synchronization with respect to other
eCAP and EPWM time-bases.
1636
Pulse-Width Modulation Subsystem (PWMSS) SPRUH73H–October 2011–Revised April 2013
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