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Ethernet Subsystem Registers
14.5.5.14 RX5_HDP Register (offset = A34h) [reset = 0h]
RX5_HDP is shown in Figure 14-102 and described in Table 14-116.
CPDMA_STATERAM RX 5 CHANNEL 5 HEAD DESC POINTER *
Figure 14-102. RX5_HDP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_HDP
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-116. RX5_HDP Register Field Descriptions
Bit Field Type Reset Description
31-0 RX_HDP R/W 0h RX DMA Head Descriptor Pointer - Writing an RX DMA Buffer
Descriptor address to this location allows RX DMA operations in the
selected channel when a channel frame is received.
Writing to these locations when they are non-zero is an error (except
at reset).
Host software must initialize these locations to zero on reset.
1337
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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