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UART/IrDA/CIR Basic Programming Model
NOTE: The UARTi.UART_FCR register is not readable.
6. Switch to register configuration mode B to access the UARTi.UART_EFR register:
Set the UARTi.UART_LCR register value to 0x00BF.
7. Load the new FIFO triggers (part 2 of 3):
Set the following bits to the desired values:
• UARTi.UART_TLR[7:4] RX_FIFO_TRIG_DMA
• UARTi.UART_TLR[3:0] TX_FIFO_TRIG_DMA
8. Load the new FIFO triggers (part 3 of 3) and the new DMA mode (part 2 of 2):
Set the following bits to the desired values:
• UARTi.UART_SCR[7] RX_TRIG_GRANU1
• UARTi.UART_SCR[6] TX_TRIG_GRANU1
• UARTi.UART_SCR[2:1] DMA_MODE_2
• UARTi.UART_SCR[0] DMA_MODE_CTL
9. Restore the UARTi.UART_EFR[4] ENHANCED_EN value saved in Step 2a.
10. Switch to register configuration mode A to access the UARTi.UART_MCR register:
Set the UARTi.UART_LCR register value to 0x0080.
11. Restore the UARTi.UART_MCR[6] TCR_TLR value saved in Step 4a.
12. Restore the UARTi.UART_LCR value saved in Step 1a.
Triggers are used to generate interrupt and DMA requests. See Section 19.3.6.1.1, Transmit FIFO Trigger,
to choose the following values:
• UARTi.UART_FCR[5:4] TX_FIFO_TRIG
• UARTi.UART_TLR[3:0] TX_FIFO_TRIG_DMA
• UARTi.UART_SCR[6] TX_TRIG_GRANU1
Triggers are used to generate interrupt and DMA requests. See Section 19.3.6.1.2, Receive FIFO Trigger,
to choose the following values:
• UARTi.UART_FCR[7:6] RX_FIFO_TRIG
• UARTi.UART_TLR[7:4] RX_FIFO_TRIG_DMA
• UARTi.UART_SCR[7] RX_TRIG_GRANU1
DMA mode enables DMA requests. See Section 19.3.6.4, FIFO DMA Mode Operation, to choose the
following values:
• UARTi.UART_FCR[3] DMA_MODE
• UARTi.UART_SCR[2:1] DMA_MODE_2
• UARTi.UART_SCR[0] DMA_MODE_CTL
19.4.1.1.3 Protocol, Baud Rate, and Interrupt Settings
To program the protocol, baud rate, and interrupt settings, perform the following steps:
1. Disable UART to access the UARTi.UART_DLL and UARTi.UART_DLH registers:
Set the UARTi.UART_MDR1[2:0] MODE_SELECT bit field to 0x7.
2. Switch to register configuration mode B to access the UARTi.UART_EFR register:
Set the UARTi.UART_LCR register value to 0x00BF.
3. Enable access to the UARTi.UART_IER[7:4] bit field:
(a) Save the UARTi.UART_EFR[4] ENHANCED_EN value.
(b) Set the UARTi.UART_EFR[4] ENHANCED_EN bit to 1.
4. Switch to register operational mode to access the UARTi.UART_IER register:
Set the UARTi.UART_LCR register value to 0x0000.
3497
SPRUH73H–October 2011–Revised April 2013 Universal Asynchronous Receiver/Transmitter (UART)
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