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Ethernet Subsystem Registers
14.5.3.6 CPTS_INTSTAT_RAW Register (offset = 20h) [reset = 0h]
CPTS_INTSTAT_RAW is shown in Figure 14-83 and described in Table 14-95.
TIME SYNC INTERRUPT STATUS RAW REGISTER
Figure 14-83. CPTS_INTSTAT_RAW Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved TS_PEND_RAW
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-95. CPTS_INTSTAT_RAW Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
0 TS_PEND_RAW R/W 0h TS_PEND_RAW int read (before enable).
Writable when int_test = 1 A one in this bit indicates that there is one
or more events in the event FIFO.
1315
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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