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I2C Registers
21.4.1.21 I2C_SA Register (offset = ACh) [reset = 0h]
I2C_SA is shown in Figure 21-36 and described in Table 21-29.
CAUTION: During an active transfer phase (between STT having been set to 1 and reception of ARDY),
no modification must be done in this register. Changing it may result in an unpredictable behavior. This
register is used to specify the addressed I2C module 7-bit or 10-bit address (slave address).
Figure 21-36. I2C_SA Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved SA
R-0h R/W-0h
7 6 5 4 3 2 1 0
SA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-29. I2C_SA Register Field Descriptions
Bit Field Type Reset Description
31-10 Reserved R 0h
9-0 SA R/W 0h Slave address.
This field specifies either: A
10-bit address coded on SA
[9:0] when XSA (Expand Slave Address, I2C_CON[8]) is set to 1.
or A
7-bit address coded on SA
[6:0] when XSA (Expand Slave Address, I2C_CON[8]) is cleared to
0.
In this case, SA
[9:7] bits must be cleared to 000 by application software.
Value after reset is low (all 10 bits).
3753
SPRUH73H–October 2011–Revised April 2013 I2C
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