EDMA3 Registers
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11.4.2.7.11 Destination FIFO Source Address Register (DFSRCn)
The destination FIFO source address register (DFSRCn) is shown in Figure 11-125 and described in
Table 11-110.
NOTE: The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC.
Figure 11-125. Destination FIFO Source Address Register (DFSRCn)
31 16
Reserved
R-0
15 0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-110. Destination FIFO Source Address Register (DFSRCn) Field Descriptions
Bit Field Value Description
31-0 Reserved 0 Reserved. Always read as 0.
11.4.2.7.12 Destination FIFO Count Register (DFCNTn)
The destination FIFO count register (DFCNTn) is shown in Figure 11-126 and described in Table 11-111.
NOTE: The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC.
Figure 11-126. Destination FIFO Count Register (DFCNTn)
31 16
BCNT
R-0
15 0
ACNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-111. Destination FIFO Count Register (DFCNTn) Field Descriptions
Bit Field Value Description
31-16 BCNT 0-FFFFh B-dimension count. Number of arrays to be transferred, where each array is ACNT in length. Count/count
remaining for destination register set. Represents the amount of data remaining to be written.
15-0 ACNT 0-FFFFh A-dimension count. Number of bytes to be transferred in first dimension count/count remaining for
destination register set. Represents the amount of data remaining to be written.
1014
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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