www.ti.com
Power, Reset, and Clock Management
8.1.12.7.1 CM_GFX_L3_CLKSTCTRL Register (offset = 0h) [reset = 2h]
CM_GFX_L3_CLKSTCTRL is shown in Figure 8-157 and described in Table 8-170.
This register enables the domain power state transition. It controls the SW supervised clock domain state
transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the
domain.
Figure 8-157. CM_GFX_L3_CLKSTCTRL Register
31 30 29 28 27 26 25 24
Reserved Reserved
R-0h R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved CLKACTIVITY_GFX_ CLKACTIVITY_GFX_
FCLK L3_GCLK
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
Reserved CLKTRCTRL
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-170. CM_GFX_L3_CLKSTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-26 Reserved R 0h
25-10 Reserved R 0h
9 CLKACTIVITY_GFX_FCL R 0h
This field indicates the state of the GFX_GCLK clock in the domain.
K
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
8 CLKACTIVITY_GFX_L3_ R 0h
This field indicates the state of the GFX_L3_GCLK clock in the
GCLK
domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
7-2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h
Controls the clock state transition of the GFX clock domain in GFX
power domain.
0x0 = NO_SLEEP : NO_SLEEP: Sleep transition cannot be initiated.
Wakeup transition may however occur.
0x1 = SW_SLEEP : SW_SLEEP: Start a software forced sleep
transition on the domain.
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up
transition on the domain.
0x3 = Reserved : Reserved.
697
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
