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Table 8-169. CM_GFX REGISTERS
Offset Acronym Register Name Section
0h CM_GFX_L3_CLKSTCTRL This register enables the domain power state transition. Section 8.1.12.7.1
It controls the SW supervised clock domain state
transition between ON-ACTIVE and ON-INACTIVE
states.
It also hold one status bit per clock input of the domain.
4h CM_GFX_GFX_CLKCTRL This register manages the GFX clocks. Section 8.1.12.7.2
Ch CM_GFX_L4LS_GFX_CLKSTCTR This register enables the domain power state transition. Section 8.1.12.7.3
L It controls the SW supervised clock domain state
transition between ON-ACTIVE and ON-INACTIVE
states.
It also hold one status bit per clock input of the domain.
10h CM_GFX_MMUCFG_CLKCTRL This register manages the MMU CFG clocks. Section 8.1.12.7.4
14h CM_GFX_MMUDATA_CLKCTRL This register manages the MMU clocks. Section 8.1.12.7.5
696
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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