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Functional Description
For the receiver-line status interrupt, the RX_FIFO_STS bit (UARTi.UART_LSR[7]) generates the
interrupt.
For the XOFF interrupt, if an XOFF flow character detection caused the interrupt, the interrupt is cleared
by an XON flow character detection. If special character detection caused the interrupt, the interrupt is
cleared by a read of the UARTi.UART_IIR register.
19.3.5.2 Wake-Up Interrupt
Wake-up interrupt is a special interrupt that works differently from other interrupts. This interrupt is
enabled when the UARTi.UART_SCR[4] RXCTSDSRWAKEUPENABLE bit is set to 1. The
UARTi.UART_IIR register is not modified when this occurs; the UARTi.UART_SSR[1]
RXCTSDSRWAKEUPSTS bit must be checked to detect a wake-up event.
When a wake-up interrupt occurs, it can be cleared only by resetting the UARTi.UART_SCR[4]
RXCTSDSRWAKEUPENABLE bit. This bit must be re-enabled (set to 1) after the current wake-up
interrupt event is processed to detect the next incoming wake-up event.
A wake-up interrupt can also occur if the WER[7] TXWAKEUPEN bit is set to 1 and one of the following
occurs:
• THR interrupt occurred if it is enabled (omitted if TX DMA request is enabled).
• TX DMA request occurred if it is enabled.
• TX_STATUS_IT occurred if it is enabled (only IrDA and CIR modes). Cannot be used with THR
interrupt.
CAUTION
Wake-Up interface implementation in IrDA mode is based on the
UARTi_SIDLEACK low-to-high transition instead of the UARTi_SIDLEACK
state.
This does not ensure wake-up event generation as expected when configured
in smart-idle mode, and the system wakes up for a short period.
19.3.5.3 IrDA Mode Interrupt Management
19.3.5.3.1 IrDA Interrupts
The IrDA function generates interrupts. All interrupts can be enabled and disabled by writing to the
appropriate bit in the interrupt enable register (UARTi.UART_IER). The interrupt status of the device can
be checked by reading the interrupt identification register (UARTi.UART_IIR).
UART, IrDA, and CIR modes have different interrupts in the UART/IrDA/CIR module and, therefore,
different UARTi.UART_IER and UARTi.UART_IIR mappings, depending on the selected mode.
IrDA modes have eight possible interrupts (see Table 19-12). The interrupt line is activated when any
interrupt is generated (there is no priority).
Table 19-12. IrDA Mode Interrupts
UART_IIR Bit Interrupt Type Interrupt Source Interrupt Reset Method
0 RHR interrupt DRDY (data ready) (FIFO Read the UART_RHR register until the
disable) interrupt condition disappears.
RX FIFO above trigger level
(FIFO enable)
1 THR interrupt TFE (UART_THR empty) Write to the UART_THR until the interrupt
(FIFO disable) condition disappears.
TX FIFO below trigger level
(FIFO enable)
3457
SPRUH73H–October 2011–Revised April 2013 Universal Asynchronous Receiver/Transmitter (UART)
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