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EDMA3 Registers
11.4.2.5 Error Registers
11.4.2.5.1 Error Register (ERRSTAT)
The error status register (ERRSTAT) is shown in Figure 11-109 and described in Table 11-94.
Figure 11-109. Error Register (ERRSTAT)
31 16
Reserved
R-0
15 4 3 2 1 0
Reserved MMRAERR TRERR Reserved BUSERR
R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 11-94. Error Register (ERRSTAT) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
3 MMRAERR MMR address error.
0 Condition is not detected.
1 User attempted to read or write to an invalid address in configuration memory map.
2 TRERR Transfer request (TR) error event.
0 Condition is not detected.
1 TR detected that violates constant addressing mode transfer (SAM or DAM is set) alignment rules or
has ACNT or BCNT == 0.
1 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
0 BUSERR Bus error event.
0 Condition is not detected.
1 EDMA3TC has detected an error at source or destination address. Error information can be read from
the error details register (ERRDET).
999
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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