Functional Description
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24.3.3 Slave Mode
McSPI is in slave mode when the bit MS of the register MCSPI_MODULCTRL is set.
In slave mode, McSPI can be connected to up to 4 external SPI master devices. McSPI handles
transactions with a single SPI master device at a time.
In slave mode, McSPI initiates data transfer on the data lines (SPIDAT[1;0]) when it receives an SPI clock
(SPICLK) from the external SPI master device.
The controller is able to work with or without a chip select SPIEN depending on
MCSPI_MODULCTRL[PIN34] bit setting. It also supports transfers without a dead cycle between two
successive words.
24.3.3.1 Dedicated Resources
In slave mode, enabling a channel that is not channel 0 has no effect. Only channel 0 can be enabled.
The channel 0, in slave mode has the following resources:
• Its own channel enable, programmable with the bit EN of the register MCSPI_CH0CTRL. This channel
should be enabled before transmission and reception. Disabling the channel, outside data word
transmission, remains under user responsibility.
• Any of the 4 ports SPIEN[3:0] can be used as a slave SPI device enable. This is programmable with
the bits SPIENSLV of the register MCSPI_CH0CONF.
• Its own transmitter register MCSPI_TX on top of the common shift register. If the transmitter register is
empty, the status bit TXS of the register MCSPI_CH0STAT is set. When McSPI is selected by an
external master (active signal on the SPIEN port assigned to channel 0), the transmitter register
content of channel0 is always loaded in shift register whether it has been updated or not. The
transmitter register should be loaded before McSPI is selected by a master.
• Its own receiver register MCSPI_RX on top of the common shift register. If the receiver register is full,
the status bit RXS of the register MCSPI_CH0STAT is set.
NOTE: The transmitter register and receiver registers of the other channels are not used. Read from
or Write in the registers of a channel other than 0 has no effect.
• Its own communication configuration with the following parameters via the register MCSPI_CH0CONF:
– Transmit/Receive modes, programmable with the bit TRM.
– Interface mode (Two data pins or Single data pin) and data pins assignment, both programmable
with the bits IS and DPE.
– SPI word length, programmable with the bits WL.
– SPIEN polarity, programmable with the bit EPOL.
– SPICLK polarity, programmable with the bit POL.
– SPICLK phase, programmable with the bit PHA.
– Use a FIFO buffer or not, programmable with FFER and FFEW, depending on transfer mode TRM.
The SPICLK frequency of a transfer is controlled by the external SPI master connected to McSPI. The bits
CLKD0 of the register 0CONF are not used in slave mode.
NOTE: The configuration of the channel can be loaded in the MCSPI_CH0CONF register only when
the channel is disabled.
• Two DMA requests events, read and write, to synchronize read/write accesses of the DMA controller
with the activity of McSPI. The DMA requests are enabled with the bits DMAR and DMAW of the
register 0CONF.
• Four interrupts events.
Figure 24-23 shows an example of four slaves wired on a single master device.
4022
Multichannel Serial Port Interface (McSPI) SPRUH73H–October 2011–Revised April 2013
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