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McASP Registers
22.4.1.28 Transmit Frame Sync Control Register (AFSXCTL)
The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX). The
AFSXCTL is shown in Figure 22-66 and described in Table 22-39.
Figure 22-66. Transmit Frame Sync Control Register (AFSXCTL)
31 16
Reserved
R-0
15 7 6 5 4 3 2 1 0
XMOD Reserved FXWID Reserved FSXM FSXP
R/W-0 R-0 R/W-0 R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-39. Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field
has no effect. If writing to this field, always write the default value for future device compatibility.
15-7 XMOD 0-1FFh Transmit frame sync mode select bits.
0 Burst mode.
1h Reserved.
2h-20h 2-slot TDM (I2S mode) to 32-slot TDM.
21h-17Fh Reserved.
180h 384-slot DIT mode.
181h-1FFh Reserved.
6-5 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field
has no effect. If writing to this field, always write the default value for future device compatibility.
4 FXWID Transmit frame sync width select bit indicates the width of the transmit frame sync (AFSX) during
its active period.
0 Single bit.
1 Single word.
3-2 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field
has no effect. If writing to this field, always write the default value for future device compatibility.
1 FSXM Transmit frame sync generation select bit.
0 Externally-generated transmit frame sync.
1 Internally-generated transmit frame sync.
0 FSXP Transmit frame sync polarity select bit.
0 A rising edge on transmit frame sync (AFSX) indicates the beginning of a frame.
1 A falling edge on transmit frame sync (AFSX) indicates the beginning of a frame.
3865
SPRUH73H–October 2011–Revised April 2013 Multichannel Audio Serial Port (McASP)
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