Texas Instruments AM335 Series Technical Reference Manual

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9.3.14 dpll_pwr_sw_status (offset = 50Ch) [reset = 0h]
dpll_pwr_sw_status is shown in Figure 9-17 and described in Table 9-24.
Figure 9-17. dpll_pwr_sw_status Register
31 30 29 28 27 26 25 24
Reserved pgoodout_ddr ponout_ddr
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
Reserved pgoodout_disp ponout_disp
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
Reserved pgoodout_per ponout_per
R-0h
7 6 5 4 3 2 1 0
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-24. dpll_pwr_sw_status Register Field Descriptions
Bit Field Type Reset Description
31-26 Reserved R 0h
25 pgoodout_ddr R 0h
Power Good status for DDR DPLL
0: Power Fault
1: Power Good
24 ponout_ddr R 0h
Power Enable status for DDR DPLL
0: Disabled
1: Enabled
23-18 Reserved R 0h
17 pgoodout_disp R 0h
Power Good status for DISP DPLL
0: Power Fault
1: Power Good
16 ponout_disp R 0h
Power Enable status for DISP DPLL
0: Disabled
1: Enabled
15-10 Reserved R 0h
9 pgoodout_per R 0h
Power Good status for PER DPLL
0: Power Fault
1: Power Good
8 ponout_per R 0h
Power Enable status for PER DPLL
0: Disabled
1: Enabled
7-0 Reserved R 0h
776
Control Module SPRUH73H–October 2011–Revised April 2013
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Texas Instruments AM335 Series Specifications

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Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English