EDMA3 Registers
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11.4.1.6.9 Secondary Event Clear Registers (SECR, SECRH)
The secondary event clear registers (SECR/SECRH) clear the status of the secondary event registers
(SER/SERH). CPU writes of 1 clear the corresponding set bits in SER/SERH. Writes of 0 have no effect.
The SECR is shown in Figure 11-86 and described in Table 11-70. The SECRH is shown in Figure 11-87
and described in Table 11-71.
Figure 11-86. Secondary Event Clear Register (SECR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: W = Write only; -n = value after reset
Table 11-70. Secondary Event Clear Register (SECR) Field Descriptions
Bit Field Value Description
31-0 En Secondary event clear register.
0 No effect.
1 Corresponding bit in the secondary event register (SER) is cleared (En = 0).
Figure 11-87. Secondary Event Clear Register High (SECRH)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E50 E49 E48
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E47 E46 E45 E44 E43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E33 E32
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: W = Write only; -n = value after reset
Table 11-71. Secondary Event Clear Register High (SECRH) Field Descriptions
Bit Field Value Description
31-0 En Secondary event clear register.
0 No effect.
1 Corresponding bit in the secondary event registers high (SERH) is cleared (En = 0).
980
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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