Appendix A
SPRUH73H–October 2011–Revised April 2013
Revision History
Table A-1 highlights the technical changes made to the SPRUH73G technical reference manual to make it
an SPRUH73H revision.
Table A-1. Document Revision History
Reference Additions/Modifications/Deletions
Chapter 1 Updated Table 1-2, Device Identification.
Introduction
Added Section 1.2, Silicon Revision Functional Differences and Enhancements.
Chapter 2 Added note to Table 2-1, L3 Memory Map, stating the first 1MB of address space 0x0-0xFFFFFF is
Memory Map inaccessible externally.
Added link to Debug Subsystem registers.
Chapter 7 GPMC
Memory Subsystem
Updated Table 7-5, GPMC Pin Multiplexing Options.
EMIF
Changed references to Peripheral Bus Burst Priority Register with Interface Configuration Register.
Updated maximum frequency in Table 7-95, EMIF Clock Signals.
Added note to Section 7.3.6, DDR2/3/mDDR PHY Registers, that the registers are write-only due to a silicon
bug.
Chapter 9 Updated Section 9.3, CONTROL_MODULE Registers.
Control Module
Chapter 10 Updated Table 10-1, L3 Master — Slave Connectivity, and Table 10-2, MConnID Assignment.
Interconnects
Chapter 11 Updated Section 14.3.2.4.1, TPTC Connectivity Attributes.
EDMA
Updated Section 11.3.12.5, EDMA3TC Configuration.
Updated registers
• Section 11.4.1.1.1, Peripheral Identification Register
• Section 11.4.1.1.3, EDMA3CC System Configuration Register
• Section 11.4.2.3, EDMA3TC System Configuration Register
• Section 11.4.2.1, Peripheral Identification Register
Chapter 13 Updated Section 13.3.3.1, Interrupts.
LCD Controller
4159
SPRUH73H–October 2011–Revised April 2013 Revision History
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