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Interrupt Controller Registers
6.5.1.16 INTC_ISR_SET0 Register (offset = 90h) [reset = 0h]
INTC_ISR_SET0 is shown in Figure 6-19 and described in Table 6-19.
This register is used to set the software interrupt bits. It is also used to read the currently active software
interrupts.
Figure 6-19. INTC_ISR_SET0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IsrSet
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-19. INTC_ISR_SET0 Register Field Descriptions
Bit Field Type Reset Description
31-0 IsrSet R/W 0h
Reads returns the currently active software interrupts, Write 1 sets
the software interrupt bits to 1
221
SPRUH73H–October 2011–Revised April 2013 Interrupts
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