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Power, Reset, and Clock Management
8.1.12.2.40 CM_CLKSEL_DPLL_PERIPH Register (offset = 9Ch) [reset = 0h]
CM_CLKSEL_DPLL_PERIPH is shown in Figure 8-123 and described in Table 8-131.
This register provides controls over the DPLL.
Figure 8-123. CM_CLKSEL_DPLL_PERIPH Register
31 30 29 28 27 26 25 24
DPLL_SD_DIV
R/W-0h
23 22 21 20 19 18 17 16
Reserved Reserved DPLL_MULT
R-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
DPLL_MULT
R/W-0h
7 6 5 4 3 2 1 0
DPLL_DIV
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-131. CM_CLKSEL_DPLL_PERIPH Register Field Descriptions
Bit Field Type Reset Description
31-24 DPLL_SD_DIV R/W 0h Sigma-Delta divider select (
2-255).
This factor must be set by s/w to ensure optimum jitter performance.
DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)] * CLKINP
/ 250), where CLKINP is the input clock of the DPLL in MHz).
Must be set with M and N factors, and must not be changed once
DPLL is locked.
0x0 = Reserved : Reserved
0x1 = Reserved1 : Reserved
23 Reserved R 0h
22-20 Reserved R 0h
19-8 DPLL_MULT R/W 0h DPLL multiplier factor (2 to 4095).
This register is automatically cleared to 0 when the DPLL_EN field in
the *CLKMODE_DPLL* register is set to select MN Bypass mode.
(equal to input M of DPLL
M=2 to
4095 => DPLL multiplies by M).
0x0 = 0 : Reserved
0x1 = 1 : Reserved
7-0 DPLL_DIV R/W 0h DPLL divider factor (0 to 255) (equal to input N of DPLL
actual division factor is N+1).
659
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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