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Power, Reset, and Clock Management
8.1.13.2 PRM_PER Registers
Table 8-184 lists the memory-mapped registers for the PRM_PER. All register offset addresses not listed
in Table 8-184 should be considered as reserved locations and the register contents should not be
modified.
Table 8-184. PRM_PER REGISTERS
Offset Acronym Register Name Section
0h RM_PER_RSTCTRL This register controls the release of the PER Domain Section 8.1.13.2.1
resets.
8h PM_PER_PWRSTST This register provides a status on the current PER power Section 8.1.13.2.2
domain state.
[warm reset insensitive]
Ch PM_PER_PWRSTCTRL Controls the power state of PER power domain Section 8.1.13.2.3
711
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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