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Functional Description
14.3.1.3.4.4 MDIO Interrupts
MDIO_LINKINT is set if there is a change in the link state of the PHY corresponding to the address in the
PHYADDRMON field of the MDIOUSERPHYSELn register and the corresponding LINKINTENB bit is
set.The MDIO_LINKINT event is also captured in the MDIOLINKINTMASKED register.When the GO bit in
the MDIOUSERACCESSn registers transitions from 1 to 0, indicating the completion of a user access,
and the corresponding USERINTMASKSET bit in the MDIOUSERINTMASKSET register is set, the
MDIO_USERINT signal is asserted 1. The MDIO_USERINT event is also captured in the
MDIOUSERINTMASKED register.
To enable the miscellaneous pulse interrupt:
The miscellaneous interrupt(s) is selected by setting one or more bits in the miscellaneous interrupt
enable register (MISC_EN).
• The Statistics interrupt is enabled by setting to 1 the STAT_INT_MASK bit in the DMA_INTMASK_SET
register.
• The HOST_PEND is enabled by setting to 1 the HOST_ERR_INT_MASK in the DMA_INTMASK_SET
register.
Upon receiving of an interrupt, software should perform the following:
• Read the Cn_MISC_STAT register to determine the source of the interrupt.
• Process the interrupt.
• Write the value 3h to the CPDMA_EOI_VECTOR register.
14.3.1.4 Embedded Memories
Memory Type Description Number of Instances
Single port 2560 by 64 RAM 3 (Packet FIFOs)
Single port 64-word by 1152-bit RAM 1 (ALE)
Single port 2048-word by 32-bit RAM 1 (CPPI)
14.3.2 CPSW_3G
The CPSW_3G GMII interfaces are compliant to the IEEE Std 802.3 Specification.
The CPSW_3G contains two CPGMAC_SL interfaces (ports 1 and 2), one CPPI 3.0 interface Host Port
(port 0), Common Platform Time Sync (CPTS), ALE Engine and CPDMA.
The top level block diagram of CPSW_3G is shown below:
1181
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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