Functional Description
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Table 11-7. Channel Options Parameters (OPT) Field Descriptions (continued)
Bit Field Value Description
17-12 TCC 0-3Fh Transfer complete code. This 6-bit code sets the relevant bit in the chaining enable register (CER [TCC]
/CERH [TCC]) for chaining or in the interrupt pending register (IPR [TCC] / IPRH [TCC]) for interrupts.
11 TCCMODE Transfer complete code mode. Indicates the point at which a transfer is considered completed for
chaining and interrupt generation.
0 Normal completion: A transfer is considered completed after the data has been transferred.
1 Early completion: A transfer is considered completed after the EDMA3CC submits a TR to the
EDMA3TC. TC may still be transferring data when the interrupt/chain is triggered.
10-8 FWID 0-7h FIFO Width. Applies if either SAM or DAM is set to constant addressing mode.
0 FIFO width is 8-bit.
1h FIFO width is 16-bit.
2h FIFO width is 32-bit.
3h FIFO width is 64-bit.
4h FIFO width is 128-bit.
5h FIFO width is 256-bit.
6h-7h Reserved.
7-4 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
3 STATIC Static set.
0 Set is not static. The PaRAM set is updated or linked after a TR is submitted. A value of 0 should be
used for DMA channels and for non-final transfers in a linked list of QDMA transfers.
1 Set is static. The PaRAM set is not updated or linked after a TR is submitted. A value of 1 should be
used for isolated QDMA transfers or for the final transfer in a linked list of QDMA transfers.
2 SYNCDIM Transfer synchronization dimension.
0 A-synchronized. Each event triggers the transfer of a single array of ACNT bytes.
1 AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes.
1 DAM Destination address mode.
0 Increment (INCR) mode. Destination addressing within an array increments. Destination is not a FIFO.
1 Constant addressing (CONST) mode. Destination addressing within an array wraps around upon
reaching FIFO width.
0 SAM Source address mode.
0 Increment (INCR) mode. Source addressing within an array increments. Source is not a FIFO.
1 Constant addressing (CONST) mode. Source addressing within an array wraps around upon reaching
FIFO width.
11.3.3.2.2 Channel Source Address (SRC)
The 32-bit source address parameter specifies the starting byte address of the source. For SAM in
increment mode, there are no alignment restrictions imposed by EDMA3. For SAM in constant addressing
mode, you must program the source address to be aligned to a 256-bit aligned address (5 LSBs of
address must be 0). The EDMA3TC will signal an error, if this rule is violated. See Section 11.3.12.3 for
additional details.
11.3.3.2.3 Channel Destination Address (DST)
The 32-bit destination address parameter specifies the starting byte address of the destination. For DAM
in increment mode, there are no alignment restrictions imposed by EDMA3. For DAM in constant
addressing mode, you must program the destination address to be aligned to a 256-bit aligned address (5
LSBs of address must be 0). The EDMA3TC will signal an error, if this rule is violated. See
Section 11.3.12.3 for additional details.
886
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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