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Ethernet Subsystem Registers
14.5.2.20 TX_INTSTAT_RAW Register (offset = 80h) [reset = 0h]
TX_INTSTAT_RAW is shown in Figure 14-48 and described in Table 14-59.
CPDMA_INT TX INTERRUPT STATUS REGISTER (RAW VALUE)
Figure 14-48. TX_INTSTAT_RAW Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
TX7_PEND TX6_PEND TX5_PEND TX4_PEND TX3_PEND TX2_PEND TX1_PEND TX0_PEND
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-59. TX_INTSTAT_RAW Register Field Descriptions
Bit Field Type Reset Description
31-8 Reserved R 0h
7 TX7_PEND R 0h
TX7_PEND raw int read (before mask).
6 TX6_PEND R 0h
TX6_PEND raw int read (before mask).
5 TX5_PEND R 0h
TX5_PEND raw int read (before mask).
4 TX4_PEND R 0h
TX4_PEND raw int read (before mask).
3 TX3_PEND R 0h
TX3_PEND raw int read (before mask).
2 TX2_PEND R 0h
TX2_PEND raw int read (before mask).
1 TX1_PEND R 0h
TX1_PEND raw int read (before mask).
0 TX0_PEND R 0h
TX0_PEND raw int read (before mask).
1279
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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