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Functional Description
24.3.2.9 Clock Ratio Granularity
By default the clock division ratio is defined by the register MCSPI_CH(I)CONF[CLKD] with power of two
granularity leading to a clock division in range 1 to 32768, in this case the duty cycle is always 50%. With
bit MCSPI_CH(I)CONF[CLKG] the clock division granularity can be changed to one clock cycle, in that
case the register MCSPI_CH(I)CTRL[EXTCLK] is concatenated with MCSPI_CH(I)CONF[CLKD] to give a
12-bit width division ratio in range 1 to 4096.
When granularity is one clock cycle (MCSPI_CH(I)CONF[CLKG] set to 1), for odd value of clock ratio the
clock duty cycle is kept to 50-50 using falling edge of clock reference CLKSPIREF.
Table 24-7. CLKSPIO High/Low Time Computation
Clock Ratio F
ratio
CLKSPIO High Time CLKSPIO Low Time
1 T
high
_ref T
low
_ref
Even ≥ 2 t_ref × (F
ratio
/2) t_ref × (F
ratio
/2)
Odd ≥ 3 t_ref × (F
ratio
/2) t_ref × (F
ratio
/2)
T_ref = CLKSPIREF period in ns. T
high
_ref = CLKSPIREF high Time period in ns. T
low
_ref = CLKSPIREF
low Time period in ns. F
ratio
= SPI clock division ratio
F
ratio
= MCSPI_CH(I)CTRL[EXTCLK].MCSPI_CH(I)CONF[CLKD] + 1
For odd ratio value the duty cycle is calculated as below:
Duty_cycle = ½
Granularity examples: With a clock source frequency of 48 MHz:
Table 24-8. Clock Granularity Examples
MCSPI_CH MCSPI_CH MCSPI_CH MCSPI_CH MCSPI_CH
(I)CTRL (I)CONF (I)CONF (I)CONF (I)CONF
Thigh Tlow Tperiod Duty Fout
EXTCLK CLKD CLKG F
ratio
PHA POL (ns) (ns) (ns) Cycle (MHz)
X 0 0 1 X X 10.4 10.4 20.8 50-50 48
X 1 0 2 X X 20.8 20.8 41.6 50-50 24
X 2 0 4 X X 41.6 41.6 83.2 50-50 12
X 3 0 8 X X 83.2 83.2 166.4 50-50 6
0 0 1 1 X X 10.4 10.4 20.8 50-50 48
0 1 1 2 X X 20.8 20.8 41.6 50-50 24
0 2 1 3 1 0 31,2 31,2 62.4 50-50 16
0 2 1 3 1 1 31,2 31,2 62.4 50-50 16
0 3 1 4 X X 41.6 41.6 83.2 50-50 12
5 0 1 81 1 0 842,4 842,4 1684.8 50-50 0.592
5 7 1 88 X X 915.2 915.2 1830.4 50-50 0.545
4013
SPRUH73H–October 2011–Revised April 2013 Multichannel Serial Port Interface (McSPI)
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