McASP Registers
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22.4.1.24 Receiver DMA Event Control Register (REVTCTL)
The receiver DMA event control register (REVTCTL) contains a disable bit for the receiver DMA event.
The REVTCTL is shown in Figure 22-62 and described in Table 22-35.
NOTE: Device-specific registers
Accessing REVTCTL not implemented on a specific device may cause improper device
operation.
Figure 22-62. Receiver DMA Event Control Register (REVTCTL)
31 16
Reserved
R-0
15 1 0
Reserved RDATDMA
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-35. Receiver DMA Event Control Register (REVTCTL) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
0 RDATDMA Receive data DMA request enable bit. If writing to this bit, always write the default value of 0.
0 Receive data DMA request is enabled.
1 Reserved
3860
Multichannel Audio Serial Port (McASP) SPRUH73H–October 2011–Revised April 2013
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