www.ti.com
DCAN Registers
23.4.11 TXRQ34 Register (offset = 8Ch) [reset = 0h]
TXRQ34 is shown in Figure 23-29 and described in Table 23-24.
The TXRQ12 to TXRQ78 registers hold the TxRqst bits of the implemented message objects. By reading
out these bits, the CPU can check for pending transmission requests. The TxRqst bit in a specific
message object can be set/reset by the CPU via the IF1/IF2 message interface registers, or by the
message handler after reception of a remote frame or after a successful transmission.
Figure 23-29. TXRQ34 Register
31 30 29 28 27 26 25 24
TxRqs[64:49]
R-0h
23 22 21 20 19 18 17 16
TxRqs[64:49]
R-0h
15 14 13 12 11 10 9 8
TxRqs[48:33]
R-0h
7 6 5 4 3 2 1 0
TxRqs[48:33]
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 23-24. TXRQ34 Register Field Descriptions
Bit Field Type Reset Description
31-16 TxRqs[64:49] R 0h
Transmission request bits (for all message objects)
0x0 = No transmission has been requested for this message object.
0x1 = The transmission of this message object is requested and is
not yet done.
15-0 TxRqs[48:33] R 0h
Transmission request bits (for all message objects)
0x0 = No transmission has been requested for this message object.
0x1 = The transmission of this message object is requested and is
not yet done.
3937
SPRUH73H–October 2011–Revised April 2013 Controller Area Network (CAN)
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
