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Power, Reset, and Clock Management
8.1.12.2.52 CM_L4_WKUP_AON_CLKSTCTRL Register (offset = CCh) [reset = 6h]
CM_L4_WKUP_AON_CLKSTCTRL is shown in Figure 8-135 and described in Table 8-143.
This register enables the domain power state transition. It controls the SW supervised clock domain state
transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the
domain.
Figure 8-135. CM_L4_WKUP_AON_CLKSTCTRL Register
31 30 29 28 27 26 25 24
Reserved Reserved
R-0h R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved Reserved
R-0h R-0h
7 6 5 4 3 2 1 0
Reserved Reserved CLKACTIVITY_L4_W CLKTRCTRL
KUP_AON_GCLK
R-0h R-0h R-1h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-143. CM_L4_WKUP_AON_CLKSTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-26 Reserved R 0h
25-14 Reserved R 0h
13-8 Reserved R 0h
7-4 Reserved R 0h
3 Reserved R 0h
2 CLKACTIVITY_L4_WKUP R 1h
This field indicates the state of the L4_WKUP clock in the domain.
_AON_GCLK
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the always on L4 clock domain.
0x0 = NO_SLEEP : Sleep transition cannot be initiated. Wakeup
transition may however occur.
0x1 = SW_SLEEP : Start a software forced sleep transition on the
domain.
0x2 = SW_WKUP : Start a software forced wake-up transition on the
domain.
0x3 = Reserved : Reserved.
671
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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