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Ethernet Subsystem Registers
14.5.2.26 RX_INTSTAT_RAW Register (offset = A0h) [reset = 0h]
RX_INTSTAT_RAW is shown in Figure 14-54 and described in Table 14-65.
CPDMA_INT RX INTERRUPT STATUS REGISTER (RAW VALUE)
Figure 14-54. RX_INTSTAT_RAW Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
RX7_THRESH_PEND RX6_THRESH_PEND RX5_THRESH_PEND RX4_THRESH_PEND RX3_THRESH_PEND RX2_THRESH_PEND RX1_THRESH_PEND RX0_THRESH_PEND
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RX7_PEND RX6_PEND RX5_PEND RX4_PEND RX3_PEND RX2_PEND RX1_PEND RX0_PEND
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-65. RX_INTSTAT_RAW Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15 RX7_THRESH_PEND R 0h
RX7_THRESH_PEND raw int read (before mask).
14 RX6_THRESH_PEND R 0h
RX6_THRESH_PEND raw int read (before mask).
13 RX5_THRESH_PEND R 0h
RX5_THRESH_PEND raw int read (before mask).
12 RX4_THRESH_PEND R 0h
RX4_THRESH_PEND raw int read (before mask).
11 RX3_THRESH_PEND R 0h
RX3_THRESH_PEND raw int read (before mask).
10 RX2_THRESH_PEND R 0h
RX2_THRESH_PEND raw int read (before mask).
9 RX1_THRESH_PEND R 0h
RX1_THRESH_PEND raw int read (before mask).
8 RX0_THRESH_PEND R 0h
RX0_THRESH_PEND raw int read (before mask).
7 RX7_PEND R 0h
RX7_PEND raw int read (before mask).
6 RX6_PEND R 0h
RX6_PEND raw int read (before mask).
5 RX5_PEND R 0h
RX5_PEND raw int read (before mask).
4 RX4_PEND R 0h
RX4_PEND raw int read (before mask).
3 RX3_PEND R 0h
RX3_PEND raw int read (before mask).
2 RX2_PEND R 0h
RX2_PEND raw int read (before mask).
1 RX1_PEND R 0h
RX1_PEND raw int read (before mask).
0 RX0_PEND R 0h
RX0_PEND raw int read (before mask).
1285
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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