EDMA3 Registers
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11.4.1.8.6 QDMA Secondary Event Clear Register (QSECR)
The QDMA secondary event clear register (QSECR) clears the status of the QDMA secondary event
register (QSER) and the QDMA event register (QER). CPU writes of 1 clear the corresponding set bits in
QSER and QER. Writes of 0 have no effect. Note that this differs from the secondary event clear register
(SECR) operation, which only clears the secondary event register (SER) bits and does not affect the event
registers.
The QSECR is shown in Figure 11-104 and described in Table 11-88.
Figure 11-104. QDMA Secondary Event Clear Register (QSECR)
31 16
Reserved
R-0
15 7 6 5 4 3 2 1 0
Reserved E7 E6 E5 E4 E3 E2 E1 E0
R-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-88. QDMA Secondary Event Clear Register (QSECR) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7-0 En QDMA secondary event clear register for channels 0-7.
0 No effect.
1 Corresponding bit in the QDMA secondary event register (QSER) and the QDMA event register (QER)
is cleared (En = 0).
992
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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