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Texas Instruments AM335 Series Technical Reference Manual

Texas Instruments AM335 Series
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USB Registers
16.5.2.35 USB0MODE Register (offset = E8h) [reset = 100h]
USB0MODE is shown in Figure 16-98 and described in Table 16-107.
Figure 16-98. USB0MODE Register
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved IDDIG
R/W-1h
7 6 5 4 3 2 1 0
IDDIG_MUX Reserved PHY_TEST LOOPBACK
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-107. USB0MODE Register Field Descriptions
Bit Field Type Reset Description
8 IDDIG R/W 1h MGC input value for iddig
0=A type
1=B type
7 IDDIG_MUX R/W 0h Multiplexer control for IDDIG signal going to the controller.
0 = IDDIG is from PHY0.
1 = IDDIG is from bit 8 (IDDIG) of this USB0MODE register.
1 PHY_TEST R/W 0h PHY test
0 = Normal mode
1 = PHY test mode
0 LOOPBACK R/W 0h Loopback test mode
0 = Normal mode
1 = Loopback test mode USB0 Mode Register
16.5.3 USB1_CTRL Registers
Table 16-108 lists the memory-mapped registers for the USB1_CTRL. All register offset addresses not
listed in Table 16-108 should be considered as reserved locations and the register contents should not be
modified.
Table 16-108. USB1_CTRL REGISTERS
Offset Acronym Register Name Section
0h USB1REV Section 16.5.3.1
14h USB1CTRL Section 16.5.3.2
18h USB1STAT Section 16.5.3.3
20h USB1IRQMSTAT Section 16.5.3.4
28h USB1IRQSTATRAW0 Section 16.5.3.5
2Ch USB1IRQSTATRAW1 Section 16.5.3.6
30h USB1IRQSTAT0 Section 16.5.3.7
34h USB1IRQSTAT1 Section 16.5.3.8
38h USB1IRQENABLESET0 Section 16.5.3.9
3Ch USB1IRQENABLESET1 Section 16.5.3.10
40h USB1IRQENABLECLR0 Section 16.5.3.11
44h USB1IRQENABLECLR1 Section 16.5.3.12
70h USB1TXMODE Section 16.5.3.13
1853
SPRUH73HOctober 2011Revised April 2013 Universal Serial Bus (USB)
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Copyright © 2011–2013, Texas Instruments Incorporated

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Texas Instruments AM335 Series Specifications

General IconGeneral
BrandTexas Instruments
ModelAM335 Series
CategoryComputer Hardware
LanguageEnglish

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