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17.1.5.2 SYSCONFIG Register (offset = 10h) [reset = 8h]
SYSCONFIG is shown in Figure 17-4 and described in Table 17-16.
This register controls the various parameters of the OCP interface
Figure 17-4. SYSCONFIG Register
31 30 29 28 27 26 25 24
Reserved
R/W-0h
23 22 21 20 19 18 17 16
Reserved
R/W-0h
15 14 13 12 11 10 9 8
Reserved
R/W-0h
7 6 5 4 3 2 1 0
Reserved SIdleMode Reserved SoftReset
R/W-0h R/W-2h R/W-4h R/W-8h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-16. SYSCONFIG Register Field Descriptions
Bit Field Type Reset Description
31-4 Reserved R/W 0h
Write 0's for future compatibility Reads returns 0
3-2 SIdleMode R/W 2h
1 Reserved R/W 4h
Write 0's for future compatibility Read returns 0
0 SoftReset R/W 8h Software reset.
This bit is automatically reset by the hardware.
During reads, it always return 0
0 = Normal : Normal mode
1 = Reset : The module is reset
3249
SPRUH73H–October 2011–Revised April 2013 Interprocessor Communication
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