McASP Registers
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22.4.1.9 Global Control Register (GBLCTL)
The global control register (GBLCTL) provides initialization of the transmit and receive sections. The
GBLCTL is shown in Figure 22-47 and described in Table 22-20.
The bit fields in GBLCTL are synchronized and latched by the corresponding clocks (ACLKX for bits 12-8
and ACLKR for bits 4-0). Before GBLCTL is programmed, you must ensure that serial clocks are running.
If the corresponding external serial clocks, ACLKX and ACLKR, are not yet running, you should select the
internal serial clock source in AHCLKXCTL, AHCLKRCTL, ACLKXCTL, and ACLKRCTL before GBLCTL
is programmed. Also, after programming any bits in GBLCTL you should not proceed until you have read
back from GBLCTL and verified that the bits are latched in GBLCTL.
Figure 22-47. Global Control Register (GBLCTL)
31 16
Reserved
R-0
15 13 12 11 10 9 8
Reserved XFRST XSMRST XSRCLR XHCLKRST XCLKRST
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 5 4 3 2 1 0
Reserved RFRST RSMRST RSRCLR RHCLKRST RCLKRST
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-20. Global Control Register (GBLCTL) Field Descriptions
Bit Field Value Description
31-13 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
12 XFRST Transmit frame sync generator reset enable bit.
0 Transmit frame sync generator is reset.
1 Transmit frame sync generator is active. When released from reset, the transmit frame sync generator
begins counting serial clocks and generating frame sync as programmed.
11 XSMRST Transmit state machine reset enable bit.
0 Transmit state machine is held in reset. AXRn pin state:
If PFUNC[n] = 0 and PDIR[n] = 1; then the serializer drives the AXRn pin to the state specified for
inactive time slot (as determined by DISMOD bits in SRCTL).
1 Transmit state machine is released from reset. When released from reset, the transmit state machine
immediately transfers data from XRBUF[n] to XRSR[n]. The transmit state machine sets the underrun
flag (XUNDRN) in XSTAT, if XRBUF[n] have not been preloaded with data before reset is released. The
transmit state machine also immediately begins detecting frame sync and is ready to transmit.
Transmit TDM time slot begins at slot 0 after reset is released.
10 XSRCLR Transmit serializer clear enable bit. By clearing then setting this bit, the transmit buffer is flushed to an
empty state (XDATA = 1). If XSMRST = 1, XSRCLR = 1, XDATA = 1, and XBUF is not loaded with new
data before the start of the next active time slot, an underrun will occur.
0 Transmit serializers are cleared.
1 Transmit serializers are active. When the transmit serializers are first taken out of reset (XSRCLR
changes from 0 to 1), the transmit data ready bit (XDATA) in XSTAT is set to indicate XBUF is ready to
be written.
9 XHCLKRST Transmit high-frequency clock divider reset enable bit.
0 Transmit high-frequency clock divider is held in reset and passes through its input as divide-by-1..
1 Transmit high-frequency clock divider is running.
8 XCLKRST Transmit clock divider reset enable bit.
0 Transmit clock divider is held in reset. When the clock divider is in reset, it passes through a divide-by-1
of its input.
1 Transmit clock divider is running.
3842
Multichannel Audio Serial Port (McASP) SPRUH73H–October 2011–Revised April 2013
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