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McASP Registers
Table 22-20. Global Control Register (GBLCTL) Field Descriptions (continued)
Bit Field Value Description
7-5 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
4 RFRST Receive frame sync generator reset enable bit.
0 Receive frame sync generator is reset.
1 Receive frame sync generator is active. When released from reset, the receive frame sync generator
begins counting serial clocks and generating frame sync as programmed.
3 RSMRST Receive state machine reset enable bit.
0 Receive state machine is held in reset.
1 Receive state machine is released from reset. When released from reset, the receive state machine
immediately begins detecting frame sync and is ready to receive.
Receive TDM time slot begins at slot 0 after reset is released.
2 RSRCLR Receive serializer clear enable bit. By clearing then setting this bit, the receive buffer is flushed.
0 Receive serializers are cleared.
1 Receive serializers are active.
1 RHCLKRST Receive high-frequency clock divider reset enable bit.
0 Receive high-frequency clock divider is held in reset and passes through its input as divide-by-1.
1 Receive high-frequency clock divider is running.
0 RCLKRST Receive high-frequency clock divider reset enable bit.
0 Receive clock divider is held in reset. When the clock divider is in reset, it passes through a divide-by-1
of its input.
1 Receive clock divider is running.
3843
SPRUH73H–October 2011–Revised April 2013 Multichannel Audio Serial Port (McASP)
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