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Functional Description
23.3.18 Message RAM
The DCAN message RAM contains message objects and parity bits for the message objects. There are
up to 64 message objects in the message RAM.
During normal operation, accesses to the message RAM are performed via the interface register sets, and
the CPU cannot directly access the message RAM.
The interface register sets IF1 and IF2 provide indirect read/write access from the CPU to the message
RAM. The IF1 and IF2 register sets can buffer control and user data to be transferred to and from the
message objects.
The third interface register set IF3 can be configured to automatically receive control and user data from
the message RAM when a message object has been updated after reception of a CAN message. The
CPU does not need to initiate the transfer from message RAM to IF3 register set.
The message handler avoids potential conflicts between concurrent accesses to message RAM and CAN
frame reception/transmission.
There are two modes where the message RAM can be directly accessed by the CPU:
• Debug/Suspend mode (see Section 23.3.18.3)
• RAM Direct Access (RDA) mode (see Section 23.3.18.4)
3917
SPRUH73H–October 2011–Revised April 2013 Controller Area Network (CAN)
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