EDMA3 Registers
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11.4.1.7.4 Interrupt Pending Register (IPR, IPRH)
If the TCINTEN and/or ITCINTEN bit in the channel option parameter (OPT) is set in the PaRAM entry
associated with the channel (DMA or QDMA), then the EDMA3TC (for normal completion) or the
EDMA3CC (for early completion) returns a completion code on transfer or intermediate transfer
completion. The value of the returned completion code is equal to the TCC bit in OPT for the PaRAM
entry associated with the channel.
When an interrupt transfer completion code with TCC = n is detected by the EDMA3CC, then the
corresponding bit is set in the interrupt pending register (IPR.In, if n = 0 to 31; IPRH.In, if n = 32 to 63).
Note that once a bit is set in the interrupt pending registers, it remains set; it is your responsibility to clear
these bits. The bits set in IPR/IPRH are cleared by writing a 1 to the corresponding bits in the interrupt
clear registers (ICR/ICRH).
The IPR is shown in Figure 11-94 and described in Table 11-78. The IPRH is shown in Figure 11-95 and
described in Table 11-79.
Figure 11-94. Interrupt Pending Register (IPR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 11-78. Interrupt Pending Register (IPR) Field Descriptions
Bit Field Value Description
31-0 In Interrupt pending for TCC = 0-31.
0 Interrupt transfer completion code is not detected or was cleared.
1 Interrupt transfer completion code is detected (In = 1, n = EDMA3TC[5:0]).
Figure 11-95. Interrupt Pending Register High (IPRH)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I63 I62 I61 I60 I59 I58 I57 I56 I55 I54 I53 I52 I51 I50 I49 I48
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I47 I46 I45 I44 I43 I42 I41 I40 I39 I38 I37 I36 I35 I34 I33 I32
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 11-79. Interrupt Pending Register High (IPRH) Field Descriptions
Bit Field Value Description
31-0 In Interrupt pending for TCC = 32-63.
0 Interrupt transfer completion code is not detected or was cleared.
1 Interrupt transfer completion code is detected (In = 1, n = EDMA3TC[5:0]).
11.4.1.7.5 Interrupt Clear Registers (ICR, ICRH)
The bits in the interrupt pending registers (IPR/IPRH) are cleared by writing a 1 to the corresponding bits
in the interrupt clear registers(ICR/ICRH). Writes of 0 have no effect. All set bits in IPR/IPRH must be
cleared to allow EDMA3CC to assert additional transfer completion interrupts.
984
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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