Transmit
format unit
Receive
Transmit
state
machine
sequencer
TDM
Transmit
machine
state
Receive
sequencer
Receive
TDM
Control
32
32
32
32
Serializer 0
Serializer 1
AXR0
AXR1
Clock
generator
Frame sync
generator
AUXCLK
Clock
generator
Frame sync
generator
AUXCLK
Transmit
Receive
Error check
ACLKX
AHCLKX
AFSX
AFSR
AHCLKR
ACLKR
AMUTE
AMUTEIN
AXEVT
AXEVTE
AXEVTO
AREVT
AREVTE
AREVTO
AXINT
ARINT
DMA events
Interrupts
Transmit
channel
Receive
channel
#
#
Pin function control
Clock check
circuit
format unit
Data port (DAT)
Configuration bus (CFG)
L3 Slow
Interconnect
L4 Standard
Interconnect
AXR15
Serializer 15
Functional Description
www.ti.com
22.3.2 Functional Block Diagram
Figure 22-2 shows the major blocks of the McASP. The McASP has independent receive/transmit clock
generators and frame sync generators.
Figure 22-2. McASP Block Diagram
A McASP has 6 serial data pins.
B AMUTEIN is not a dedicated McASP pin, but typically comes from one of the external interrupt pins.
3774
Multichannel Audio Serial Port (McASP) SPRUH73H–October 2011–Revised April 2013
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Copyright © 2011–2013, Texas Instruments Incorporated
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