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CONTROL_MODULE Registers
9.3.73 ecap_evt_capt Register (offset = FD4h) [reset = 0h]
ecap_evt_capt is shown in Figure 9-76 and described in Table 9-83.
Figure 9-76. ecap_evt_capt Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved ecap2_evtcapt
R-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved ecap1_evtcapt
R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved ecap0_evtcapt
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-83. ecap_evt_capt Register Field Descriptions
Bit Field Type Reset Description
31-21 Reserved R 0h
20-16 ecap2_evtcapt R/W 0h ECAP2 event capture mux
15-13 Reserved R 0h
12-8 ecap1_evtcapt R/W 0h ECAP1 event capture mux
7-5 Reserved R 0h
4-0 ecap0_evtcapt R/W 0h ECAP0 event capture mux
837
SPRUH73H–October 2011–Revised April 2013 Control Module
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