Power, Reset, and Clock Management
www.ti.com
8.1.12.2.45 CM_WKUP_WKUP_M3_CLKCTRL Register (offset = B0h) [reset = 2h]
CM_WKUP_WKUP_M3_CLKCTRL is shown in Figure 8-128 and described in Table 8-136.
This register manages the WKUP M3 clocks.
Figure 8-128. CM_WKUP_WKUP_M3_CLKCTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved STBYST Reserved
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-136. CM_WKUP_WKUP_M3_CLKCTRL Register Field Descriptions
Bit Field Type Reset Description
31-19 Reserved R 0h
18 STBYST R 0h
Module standby status.
0x0 = Func : Module is functional (not in standby)
0x1 = Standby : Module is in standby
17-2 Reserved R 0h
1-0 MODULEMODE R 2h
Control the way mandatory clocks are managed.
664
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
