DMTimer
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20.1.3.1.6 Timer Counting Rate
The timer counter is composed of a prescaler stage and a timer counter. Prescaler stage is clocked with
the timer clock and acts as a clock divider for the timer counter stage. The ratio can be managed by
accessing the ratio definition field of the control register (PTV and PRE of TCLR). See Table 20-7.
The timer rate is defined by:
• The value of the prescaler fields (PRE and PTV of TCLR register)
• The value loaded into the Timer Load Register (TLDR).
Table 20-7. Prescaler Clock Ratios Value
PRE PTV Divisor (PS)
0 X 1
1 0 2
1 1 4
1 2 8
1 3 16
1 4 32
1 5 64
1 6 128
1 7 256
The timer rate equation is as follows:
(FFFF FFFFh – TLDR + 1) × timer Clock period × Clock Divider (PS)
With timer Clock period = 1/ timer Clock frequency and PS = 2(PTV + 1).
As an example, if we consider a timer clock input of 32 kHz, with a PRE field equal to 0, the timer output
period is:
Table 20-8. Value and Corresponding Interrupt Period
TLDR Interrupt period
0000 0000h 37 h
FFFF 0000h 2 s
FFFF FFF0h 500 us
FFFF FFFEh 62.5 us
20.1.3.1.7 Dual Mode Timer Under Emulation
During emulation mode (when PINSUSPENDN signal is active), the timer can/cannot continue running
according to the value of the EmuFree bit of the timer OCP configuration register (TIOCP_CFG).
If EmuFree is 1, timer execution is not stopped and, regardless of the value of PINSUSPENDN signal, and
the interrupt assertion is still generated when overflow is reached.
If EmuFree is 0, counters (prescaler/timer) are frozen and an increment start occurs again as soon as
PINSUSPENDN becomes inactive. The asynchronous input pin is internally synchronized on 2 TIMER
clock rising edges.
3562
Timers SPRUH73H–October 2011–Revised April 2013
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