Texas Instruments AM335 Series Technical Reference Manual

Integer
Core
Neon
Core
L1 I
32KB w/SED
L1 D
32KB w/SED
L2
256KB w/ECC
Cortex A8
AXI2OCP
275 MHz
OCM RAM
64 KB
ROM
176 KB
128
64
I2ASYNC
550 MHz
I2ASYNC
550 MHz
AINTC
275 MHz
32
ICE Crusher
OCP2
ATB
128
64
OCP Master 0 OCP Master 1
To L3 To L3
32
Debug Bus
(OCP)
MPU
Subsystem
System
Interrupts
MPU PLL
CLK_M_OSC
Frm Master OSC
128
64
T2ASYNC
200 MHz
T2ASYNC
200 MHz
ETMSOC
Internal SRAM
64K
www.ti.com ARM Cortex-A8 MPU Subsystem
3.1 ARM Cortex-A8 MPU Subsystem
The Microprocessor Unit (MPU) subsystem of the device handles transactions between the ARM core
(ARM® Cortex™-A8 Processor), the L3 interconnect, and the interrupt controller (INTC). The MPU
subsystem is a hard macro that integrates the ARM® Cortex™-A8 Processor with additional logic for
protocol conversion, emulation, interrupt handling, and debug enhancements.
Cortex™-A8 is an ARMv7 compatible, dual-issue, in-order execution engine with integrated L1 and L2
caches with NEON™ SIMD Media Processing Unit.
An Interrupt Controller is included in the MPU subsystem to handle host interrupt requests in the system.
The MPU subsystem includes CoreSight compliant logic to allow the Debug Sub-system access to the
CortexA8 debug and emulation resources, including the Embedded Trace Macrocell.
The MPU subsystem has three functional clock domains, including a high-frequency clock domain used by
the Cortex™-A8. The high-frequency domain is isolated from the rest of the system by asynchronous
bridges.
Figure 3-1 shows the high-level block diagram of the MPU subsystem.
Figure 3-1. Microprocessor Unit (MPU) Subsystem
165
SPRUH73H–October 2011–Revised April 2013 ARM MPU Subsystem
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Texas Instruments AM335 Series Specifications

General

Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English