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Power, Reset, and Clock Management
8.1.13 Power Management Registers
8.1.13.1 PRM_IRQ Registers
Table 8-178 lists the memory-mapped registers for the PRM_IRQ. All register offset addresses not listed
in Table 8-178 should be considered as reserved locations and the register contents should not be
modified.
Table 8-178. PRM_IRQ REGISTERS
Offset Acronym Register Name Section
0h REVISION_PRM This register contains the IP revision code for the PRCM Section 8.1.13.1.1
4h PRM_IRQSTATUS_MPU This register provides status on MPU interrupt events. Section 8.1.13.1.2
An event is logged whether interrupt generation for the
event is enabled or not.
SW is required to clear a set bit by writing a '1' into the
bit-position to be cleared.
8h PRM_IRQENABLE_MPU This register is used to enable and disable events used Section 8.1.13.1.3
to trigger MPU interrupt activation.
Ch PRM_IRQSTATUS_M3 This register provides status on MPU interrupt events. Section 8.1.13.1.4
An event is logged whether interrupt generation for the
event is enabled or not.
SW is required to clear a set bit by writing a '1' into the
bit-position to be cleared.
10h PRM_IRQENABLE_M3 This register is used to enable and disable events used Section 8.1.13.1.5
to trigger MPU interrupt activation.
705
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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