Texas Instruments AM335 Series Technical Reference Manual

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7.3.5.2 STATUS Register (offset = 4h) [reset = 0h]
STATUS is shown in Figure 7-92 and described in Table 7-112.
Figure 7-92. STATUS Register
31 30 29 28 27 26 25 24
reg_be reg_dual_clk_mode reg_fast_init Reserved
R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved reg_phy_dll_ready Reserved
R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-112. STATUS Register Field Descriptions
Bit Field Type Reset Description
31 reg_be R 0h Big Endian.
Reflects the value on the config_big_endian port that defines
whether the EMIF is in big or little endian mode.
0 = Little endian.
1 = Big endian.
30 reg_dual_clk_mode R 0h Dual Clock mode.
Reflects the value on the config_dual_clk_mode port that defines
whether the ocp_clk and m_clk are asynchronous.
0 = ocp_clk = m_clk.
1 = Asynchronous ocp_clk and m_clk.
29 reg_fast_init R 0h Fast Init.
Reflects the value on the config_fast_init port that defines whether
the EMIF fast initialization mode has been enabled.
0 = Fast init disabled.
1 = Fast init enabled.
28-3 Reserved R 0h
2 reg_phy_dll_ready R 0h DDR PHY Ready.
Reflects the value on the phy_ready port (active high) that defines
whether the DDR PHY is ready for normal operation.
1-0 Reserved R 0h
425
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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Texas Instruments AM335 Series Specifications

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Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English