Texas Instruments AM335 Series Technical Reference Manual

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7.3.3.4.2 Address Mapping when REG_IBANK_POS = 1 and REG_EBANK_POS = 0
For REG_IBANK_POS = 1 and REG_EBANK_POS = 0, the interleaving of banks within a device (per chip
select) is limited to 4 banks. However, it can still interleave banks between the two chip selects. Thus, the
DDR2/3/mDDR controller can keep a maximum of 16 banks (8 internal banks across 2 chip selects) open
at a time, but can only interleave among eight of them.
Table 7-101. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=1 and
REG_EBANK_POS=0
Logical Address
Bank Address[2] Row Address Chip Select Bank Address[1:0] Column Address
# of bits defined by # of bits defined by # of bits defined by # of bits defined by # of bits defined by
IBANK of SDRCR RSIZE of SDRCR EBANK of SDRCR IBANK of SDRCR PAGESIZE of SDRCR
IBANK=0 => 0 bits RSIZE=0 => 9 bits EBANK=0 => 0 bits IBANK=0 => 0 bits PAGESIZE=0 => 8 bits
IBANK=1 => 0 bits RSIZE=1 => 10 bits EBANK=1 => 1 bit IBANK=1 => 1 bit PAGESIZE=1 => 9 bits
IBANK=2 => 0 bits RSIZE=2 => 11 bits IBANK=2 => 2 bits PAGESIZE=2 => 10 bits
IBANK=3 => 1 bit RSIZE=3 => 12 bits IBANK=3 => 3 bits PAGESIZE=3 => 11 bits
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits
7.3.3.4.3 Address Mapping when REG_IBANK_POS=2 and REG_EBANK_POS = 0
For REG_IBANK_POS=2 and REG_EBANK_POS = 0, the interleaving of banks within a device (per chip
select) is limited to 2 banks. However, it can still interleave banks between the two chip selects. Thus, the
DDR2/3/mDDR controller can keep a maximum of 16 banks (eight internal banks across 2 chip selects)
open at a time, but can only interleave among four of them.
Table 7-102. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=2 and
REG_EBANK_POS=0
Logical Address
Bank Address[2:1] Row Address Chip Select Bank Address[0] Column Address
# of bits defined by # of bits defined by # of bits defined by # of bits defined by # of bits defined by
IBANK of SDRCR RSIZE of SDRCR EBANK of SDRCR IBANK of SDRCR PAGESIZE of SDRCR
IBANK=0 => 0 bits RSIZE=0 => 9 bits EBANK=0 => 0 bits IBANK=0 => 0 bits PAGESIZE=0 => 8 bits
IBANK=1 => 0 bits RSIZE=1 => 10 bits EBANK=1 => 1 bit IBANK=1 => 1 bit PAGESIZE=1 => 9 bits
IBANK=2 => 1 bit RSIZE=2 => 11 bits IBANK=2 => 1 bit PAGESIZE=2 => 10 bits
IBANK=3 => 2 bits RSIZE=3 => 12 bits IBANK=3 => 1 bit PAGESIZE=3 => 11 bits
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits
7.3.3.4.4 Address Mapping when REG_IBANK_POS= 3 and REG_EBANK_POS = 0
For REG_IBANK_POS= 3 and REG_EBANK_POS = 0, the DDR2/3/mDDR controller cannot interleave
banks within a device (per chip select). However, it can still interleave banks between the two chip selects.
Thus, the DDR2/3/mDDR controller can keep a maximum of 16 banks (8 internal banks across 2 chip
selects) open at a time, but can only interleave among two of them.
411
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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Texas Instruments AM335 Series Specifications

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Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English