USB Subsystem
L3 Slow
Interconnect
USB0 Pads
MPU
Subsystem
Interrupts
usbss_intr
USB0_DP
PRCM
L3 Slow
Interconnect
L3 Slow
Interconnect
ocp_clk
USB_GCLK (100 MHZ)
PHY
USB0_DM
USB0_DRVVBUS
PHY
usb_fifo1
USB
2.0
UTMI
UTMI
tx1
rx1
usbslv1
usb_fifo0
tx0
rx0
usbslv0
SCR
S
S
S
S
S
S
S
S
CPPI
DMA
CPPI
DMA
Scheduler
S
S
MM
Mstr0
Mstr1
SLV
OHCP
Bridge
Regs
qmgr_slv
S
m_vbusp
qmgr_slv
S
mmr
IPG
modirq
M
cdma_cfg
cdma_fifo
cdma_mem
usbs0_intr
usb1_intr
USB1 Pads
USB1_DP
USB1_DM
USB1_DRVVBUS
refclk
refclk
CORE_CLKOUTM4
slv0_Swakeup
USB0_VBUS
USB1_VBUS
USB0_CE
USB1_CE
WakeM3
usb0_wout
usb1_wout
/2
OHCP
Bridge
Queue
MGR
OHCP
Bridge
USB
2.0
960 MHz
Per_PLL
USB0_ID
USB1_ID
Integration
www.ti.com
16.2 Integration
This device implements the USB2.0 OTG dual port module and PHY for interfacing to USB as a peripheral
or host.
Figure 16-1 shows the integration of the USB module on this device.
Figure 16-1. USB Integration
16.2.1 USB Connectivity Attributes
The USB module itself has a very large number of interrupt outputs. For ease of integration, these outputs
are all routed to a pair of interrupt aggregators. These aggregator blocks generate a single interrupt on the
first occurrence of any interrupt from the USB or DMA logic of the module.
Table 16-1. USB Connectivity Attributes
Attributes Type
Power domain Peripheral Domain
Clock domain PD_PER_L3S_GCLK (OCP)
CLKDCOLDO (PHY)
Reset signals DEF_DOM_RST_N
USB_POR_N
Idle/Wakeup signals Smart idle
Wakeup
Standby
1694
Universal Serial Bus (USB) SPRUH73H–October 2011–Revised April 2013
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Copyright © 2011–2013, Texas Instruments Incorporated
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