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UART Registers
19.5.1.51 FREQ_SEL Register
The FREQ_SEL register (FREQ_SEL) is shown in Figure 19-84 and described in Table 19-83.
Figure 19-84. FREQ_SEL Register
31 8 7 0
Reserved FREQ_SEL
R-0 R/W-1A
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-83. FREQ_SEL Register Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved.
7-0 FREQ_SEL 1A Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value
is set. Must be equal or higher then 6.
3547
SPRUH73H–October 2011–Revised April 2013 Universal Asynchronous Receiver/Transmitter (UART)
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