Texas Instruments AM335 Series Technical Reference Manual

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8.1.12.1.61 CM_PER_CLK_24MHZ_CLKSTCTRL Register (offset = 150h) [reset = 2h]
CM_PER_CLK_24MHZ_CLKSTCTRL is shown in Figure 8-83 and described in Table 8-90.
This register enables the clock domain state transition. It controls the SW supervised clock domain state
transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the
domain.
Figure 8-83. CM_PER_CLK_24MHZ_CLKSTCTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_CLK_2 Reserved CLKTRCTRL
4MHZ_GCLK
R-0h R-0h R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-90. CM_PER_CLK_24MHZ_CLKSTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-5 Reserved R 0h
4 CLKACTIVITY_CLK_24M R 0h
This field indicates the state of the 24MHz clock in the domain.
HZ_GCLK
0x0 = Inact
0x1 = Act
3-2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h
Controls the clock state transition of the 24MHz clock domain.
0x0 = NO_SLEEP : NO_SLEEP: Sleep transition cannot be initiated.
Wakeup transition may however occur.
0x1 = SW_SLEEP : SW_SLEEP: Start a software forced sleep
transition on the domain.
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up
transition on the domain.
0x3 = Reserved : Reserved.
8.1.12.2 CM_WKUP Registers
Table 8-91 lists the memory-mapped registers for the CM_WKUP. All register offset addresses not listed
in Table 8-91 should be considered as reserved locations and the register contents should not be
modified.
Table 8-91. CM_WKUP REGISTERS
Offset Acronym Register Name Section
0h CM_WKUP_CLKSTCTRL This register enables the domain power state transition. Section 8.1.12.2.1
It controls the SW supervised clock domain state
transition between ON-ACTIVE and ON-INACTIVE
states.
It also hold one status bit per clock input of the domain.
4h CM_WKUP_CONTROL_CLKCTRL This register manages the Control Module clocks. Section 8.1.12.2.2
8h CM_WKUP_GPIO0_CLKCTRL This register manages the GPIO0 clocks. Section 8.1.12.2.3
611
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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Texas Instruments AM335 Series Specifications

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Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English