Ethernet Subsystem Registers
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14.5.2.49 RX7_FREEBUFFER Register (offset = FCh) [reset = 0h]
RX7_FREEBUFFER is shown in Figure 14-77 and described in Table 14-88.
CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 7
Figure 14-77. RX7_FREEBUFFER Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
RX_FREEBUFFER
W-0h
7 6 5 4 3 2 1 0
RX_FREEBUFFER
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-88. RX7_FREEBUFFER Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15-0 RX_FREEBUFFER W 0h Rx Free Buffer Count - This field contains the count of free buffers
available.
The rx_pendthresh value is compared with this field to determine if
the receive threshold pending interrupt should be asseted (if
enabled).
This is a write to increment field.
This field rolls over to zero on overflow.
If receive threshold pending interrupts are used, the host must
initialize this field to the number of available buffers (one register per
channel).
The port decrements (by the number of buffers in the received
frame) the associated channel register for each received frame.
This is a write to increment field.
The host must write this field with the number of buffers that have
been freed due to host processing.
14.5.3 CPSW_CPTS Registers
Table 14-89 lists the memory-mapped registers for the CPSW_CPTS. All register offset addresses not
listed in Table 14-89 should be considered as reserved locations and the register contents should not be
modified.
Table 14-89. CPSW_CPTS REGISTERS
Offset Acronym Register Name Section
0h CPTS_IDVER IDENTIFICATION AND VERSION REGISTER Section 14.5.3.1
4h CPTS_CONTROL TIME SYNC CONTROL REGISTER Section 14.5.3.2
Ch CPTS_TS_PUSH TIME STAMP EVENT PUSH REGISTER Section 14.5.3.3
10h CPTS_TS_LOAD_VAL TIME STAMP LOAD VALUE REGISTER Section 14.5.3.4
14h CPTS_TS_LOAD_EN TIME STAMP LOAD ENABLE REGISTER Section 14.5.3.5
20h CPTS_INTSTAT_RAW TIME SYNC INTERRUPT STATUS RAW REGISTER Section 14.5.3.6
24h CPTS_INTSTAT_MASKED TIME SYNC INTERRUPT STATUS MASKED Section 14.5.3.7
REGISTER
28h CPTS_INT_ENABLE TIME SYNC INTERRUPT ENABLE REGISTER Section 14.5.3.8
1308
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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